mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 619

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
SYNL—Sync Length (Transparent Mode Only)
This field determines the operation of the SCCx receiver that is configured for totally
transparent operation.
RTSM—RTS Mode
This bit indicates the mode of the request-to-send modem signal. It can be changed on-the-
fly.
RSYN—Receive Synchronization Timing (Transparent Mode Only)
GSMR_L
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
00 = The sync pattern in the DSR (described in Section 16.9.4 Data Synchronization
01 = 4-bit sync. The receiver synchronizes on a 4-bit sync pattern stored in the DSR.
10 = 8-bit sync. The receiver synchronizes on an 8-bit sync pattern stored in the DSR.
11 = 16-bit sync. The receiver synchronizes on a 16-bit sync pattern stored in the DSR.
0 = Send idles between frames as defined by the protocol and the TEND bit in the
1 = Send flags/syncs between frames according to the protocol. RTSx is always
0 = Normal operation.
1 = If the CDS bit is set to 1, then the CDx signal must be asserted on the second bit
GSMR_L. RTSx is negated between frames (default).
asserted when a serial communication controller is enabled.
of the receive frame, rather than the first.
Register ) is not used. An external sync signal is used instead.
This character and additional syncs can be programmed to be stripped using the
Sync character in the parameter RAM. The transmitter transmits the entire
contents of the DSR prior to each frame.
The transmitter transmits the entire contents of the DSR prior to each frame.
The transmitter transmits the DSR prior to each frame.
RES
R/W
16
0
0
RDCR
R/W
0
17
1
EDGE
R/W
0
18
2
Freescale Semiconductor, Inc.
RENC
For More Information On This Product,
R/W
R/W
TCI
19
3
0
0
20
MPC823 REFERENCE MANUAL
4
TSNC
R/W
0
Go to: www.freescale.com
21
5
TENC
RINV
R/W
R/W
22
(IMMR & 0xFFF0000) + 0xA20
(IMMR & 0xFFF0000) + 0xA22
6
0
0
TINV
R/W
23
7
0
24
8
DIAG
R/W
0
R/W
TPL
25
9
0
Communication Processor Module
ENR
R/W
10
26
0
ENT
R/W
11
27
0
TPP
R/W
0
12
28
TEND
R/W
13
29
0
MODE
R/W
0
14
30
TDCR
R/W
16-167
0
15
31

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