mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 433

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

3. Translate the timing diagrams into RAM words for each type of memory access. The
4. Define the UPMA (or UPMB) parameters that control the memory system in the
bottom half of the figures represent the RAM array contents that handle each of the
possible cycles and each column represents a different word in the RAM array. A
blank cell in each figure indicates a “don’t care” bit, which is typically programmed to
logic 1 to conserve power.
following sequence. For additional details, see Table 15-10.
— Program the RAM array using the memory command register (MCR) and
— Initialize the option and base registers of the specific bank according to the
— Use the MS field of the option register to select the machine you have chosen
— Program the MAMR to select the number of columns and refresh timer
GPLA4DIS
memory data register (MDR). The RAM word must be written into the MDR
before you issue the WRITE command to the MCR. Repeat this step for all RAM
word entries.
address mapping of the DRAM device you have chosen.
to control the cycles. Notice that the SAM bit in the option register determines
address multiplexing for the first clock cycle and subsequent cycles are
controlled by the UPM RAM words. Also notice that the AMX field in the UPM
RAM word controls the address multiplexing for the next clock cycle rather than
the current cycle.
parameters.
FIELD
WLFA
PTAE
RLFA
AMA
DSA
SAM
PTP
PTA
MS
WP
PS
BI
Freescale Semiconductor, Inc.
REGISTER
For More Information On This Product,
Table 15-10. UPMA Register Settings
MPTPR
MAMR
MAMR
MAMR
MAMR
MAMR
MAMR
MAMR
OR1
OR1
BR1
BR1
BR1
MPC823 REFERENCE MANUAL
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00000010
00001100
VALUE
0011
0011
001
10
00
01
0
1
0
1
0
Selects UPMA
Selects 32-Bit Bus Width
Allows Read and Write Accesses
Prescaler Divided by Two
15.6 s at a 25MHz Clock
Enables Periodic Timer A
Selects Nine Column Address Pins
Selects Two Disable Timer Clock Cycles
Disables the UPWAITA Signal
Selects Three Loop Iterations for Read
Selects Three Loop Iterations for Write
Selects Column Address on First Cycle
Supports Burst Accesses
COMMENTS
Memory Controller
15-77