mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 732

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
R—Ready
Bits 1, 5, and 7–11—Reserved
These bits are reserved and must be set to 0.
W—Wrap (Final Buffer Descriptor in Table)
I—Interrupt
L—Last
CM—Continuous Mode
CT—CTS Lost
In NMSI mode, this bit indicates that CTS is lost during frame transmission. If data from more
than one buffer is currently in the FIFO when this error occurs, this bit is set in the currently
open TX buffer descriptor. These bits are written by the SCCx ASYNC HDLC controller after
it finishes transmitting the associated data buffer.
0 = The data buffer associated with this buffer descriptor is not ready for transmission.
1 = The data buffer, which you have prepared for transmission, is not transmitted yet
0 = This is not the last buffer descriptor in the TX buffer descriptor table.
1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer is
0= The TXB bit in the SCCE–ASYNC HDLC register is not set after this buffer is used.
1= The TXB bit in the SCCE–ASYNC HDLC register is set when this buffer is
0= This is not the last buffer in the current frame.
1= This is the last buffer in the current frame. The proper CRC and closing FLAG are
0 = Normal operation.
1 = The R bit is not cleared by the communication processor module after this buffer
You are free to manipulate this buffer descriptor or its associated data buffer. The
communication processor module clears this bit after the buffer is transmitted or
after an error condition is encountered.
or is currently being transmitted. You cannot write any fields of this buffer descriptor
once this bit is set.
used, the communication processor module receives incoming data into the first
buffer descriptor that TBASE points to in the table. The number of TX buffer
descriptors in this table are programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
transmitted by the SCCx ASYNC HDLC controller.
transmitted after the last byte is transmitted.
descriptor is closed, thus allowing the associated data buffer to be automatically
retransmitted the next time the communication processor module accesses this
buffer descriptor. However, the R bit is cleared if an error occurs during
transmission, regardless of how the CM bit is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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