mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 202

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Instruction Cache
Bits 25–31—Reserved
These bits are reserved and must be set to 0.
9.4.7 Instruction Cache Write
Instruction cache write is only enabled when the MPC823 is in test mode.
9.5 RESTRICTIONS
Zero wait state devices that are placed on the internal bus are considered to be in the
cache-inhibited memory region and the hardware correct operation trusts the software to
follow the exact steps mentioned in Section 9.7 Updating Code And Memory Region
Attributes. It is not recommended that you perform LOAD & LOCK from zero wait state
devices that are placed on the internal bus, especially since it is not guaranteed that the data
will be fetched from the instruction cache. In most cases, it is fetched from the device, but
found in the instruction cache.
9.6 INSTRUCTION CACHE COHERENCY
Cache coherency in a multiprocessor environment is maintained by the software and
supported by the invalidation mechanism as described above. All instruction storage is
considered to be coherent, not required, mode.
9.7 UPDATING CODE AND MEMORY REGION ATTRIBUTES
To update the code or change the programming of the memory regions in the chip-select
logic, follow these steps:
9.8 RESET SEQUENCE
To simplify the debug task of the system, the instruction cache is only disabled during
hardware reset (IC_CST
the instruction cache prior to the event that asserts the reset. To ensure proper operation of
the instruction cache after reset, the UNLOCK ALL, INVALIDATE ALL, and
INSTRUCTION CACHE ENABLE commands must be executed.
9.9 DEBUG SUPPORT
The MPC823 can be debugged either in debug mode or by a software monitor debugger. In
both cases, the core of the MPC823 CPU asserts the internal freeze (FRZ) signal. When
FRZ is asserted the instruction cache treats all misses as if they were from cache-inhibited
regions and, assuming the debug routine is not in the instruction cache, the cache state
remains exactly the same. When FRZ is asserted, hits are still read from the array and the
1. Update the code and change the memory region programming in the chip-select logic.
2. Execute the sync instruction to ensure that the update/change operation has finished.
3. Unlock all locked lines that contain code that was updated.
4. Invalidate all lines that contain code that was updated.
5. Execute the isync instruction.
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