mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 220

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

A successful TLB hit occurs if the incoming effective address matches the EPN stored in a
valid TLB entry and the CASID value stored in the M_CASID register matches the entry’s
ASID field. At the same time, the subpage validity flag is set for the subpage pointed to by
the incoming effective address. If a hit is detected, the content of the real page number is
concatenated with the appropriate number of least-significant bits from the effective address
to form the real address that is then sent to the cache and memory system.
11.3 PROTECTION
Access control is assigned on a page-by-page basis and any further manipulation is
conducted on a group basis.
Figure 11-1. Block Diagram of Effective-to-Real Address Translation For 4K Pages
TRANSLATION
ENABLED
MSRPR
8-ENTRY FULLY ASSOCIATIVE ARRAY
TRANSLATION LOOKASIDE BUFFER
(FROM M_CASID)
32-BIT REAL ADDRESS
CASID
REAL PAGE NUMBER
Freescale Semiconductor, Inc.
32-BIT EFFECTIVE
For More Information On This Product,
ADDRESS
PAGE
TRANSLATION
20
MPC823 REFERENCE MANUAL
20
ENABLED
20
Go to: www.freescale.com
BYTE
BYTE
12
12
32-BIT LOGICAL
PROTECTION
ADDRESS
LOOKUP
TABLE
GROUP NUMBER
PROTECTION
PAGE PROTECTION
NO ACCESS
FREE ACCESS
IMPLEMENTATION SPECIFIC
TLB MISS INTERRUPTS
Memory Management Unit
TO CORE
ERROR INTERRUPTS
IMPLEMENTATION
EXCEPTION
SPECIFIC
TO CORE
LOGIC
11-3