mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 184

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Instruction Execution Timing
In this example, the addic instruction is dependent on the sub rather than on the mulli .
Although the writeback of the mulli is delayed two clocks, there is no bubble in the execution
stream.
8.2.2.2 PRIVATE WRITEBACK BUS LOAD
lwz
sub
cror
and
xor
or
The load and the xor writeback in the same clock since they use the writeback bus in two
different ticks.
GCLK1
FETCH
DECODE
READ + EXECUTE
WRITEBACK
L ADDRESS DRIVE
L DATA
CACHE ADDRESS
LOAD WRITEBACK
E ADDRESS
E DATA
r12,64 (SP)
r5,r5,3
4,14,1
r3,r4.r5
r4,r3,r5
r6,r12.r3
Figure 8-4. Example of a Private Writeback Bus Load
LWZ
Freescale Semiconductor, Inc.
For More Information On This Product,
LOAD
SUB
MPC823 REFERENCE MANUAL
LOAD
Go to: www.freescale.com
LWZ
SUB
CROR
SUB
LWZ
CROR
SUB
AND
CROR
AND
CR
XOR
LWZ
AND
XOR
AND
ORI
LWZ
XOR
LWZ
ORI
XOR
LWZ
MOTOROLA
ORI
ORI

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