mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 213

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Data Cache
10.4 OPERATING THE DATA CACHE
The data cache is a three-state design. Two bits are included in each cache line to maintain
the line’s state information. The status bits keep track of whether or not the line is valid or if
it has been modified relative to memory. These modes are invalid, modified-valid, and
unmodified-valid.
10.4.1 Data Cache Read
There are two possible outcomes of a data cache read:
10.4.2 Data Cache Write
The cache operates in either writethrough or copyback mode, depending on how the
memory management unit is programmed. If two logical blocks map to the same physical
block, it is considered a programming error for them to specify different cache write policies.
• Read Hit—On a cache hit, the requested word is immediately transferred to the
• Read Miss—A line in the cache is selected to hold the data that will be fetched from
load/store unit and the LRU state of the set is updated. No state transition occurs and
the access time is 1 clock (zero wait state).
memory. The selection algorithm gives first priority to invalid lines and if both lines are
invalid, the way zero line is selected first. If neither of the two candidate lines in the
selected set is invalid, then one of the lines is selected by the LRU algorithm for
replacement. If the selected line is valid-modified (dirty), then it is kept in a special buffer
to be written out (flushed) to memory or a later time.
Subsequently, the address of the missed entry is sent to the system interface unit with
a request to retrieve the cache line. The system interface unit arbitrates for the bus and
initiates a 4-word burst transfer read request. The transfer begins with the aligned word
containing the missed data, followed by the remaining word in the line, then by the word
at the beginning of the line (wraparound). As the missed word is received from the bus,
it is delivered (forwarded) directly to the load/store unit. When the line has been fully
received, it is written into the cache. The data cache supports further requests as long
as they hit in the cache immediately after the arrival of the critical word.
After the line with the requested data has been brought from memory, the dirty line kept
in the buffer is sent to the system interface unit to be written out (flushed) to memory. If
a bus error is detected during the fetch of the missed “critical word”, a machine check
interrupt is generated. If a bus error occurs on any other word in the line transfer, the
line is marked invalid. On the other hand, if no bus error is encountered, the cache line
is marked unmodified-valid. If a bus error is detected during the dirty line flush, a
machine check interrupt is generated (the dirty line flush error is an imprecise interrupt).
For more information about reading the address and data of a line, see
Section 10.3.3.3 Reading the Cache Structures .
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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