mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 277

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
System Interface Unit
Bits 16–31—Reserved
These bits are reserved and must be set to 0.
12.3.3.2 SIU INTERRUPT MASK REGISTER. The 32-bit read/write SIU interrupt mask
(SIMASK) register contains bits that individually correspond to the interrupt request bits in
the SIPEND register. When a bit is set, it enables the generation of an interrupt request to
the core. SIMASK is updated by the software and cleared at reset. It is the responsibility of
the software to determine which of the interrupt sources are enabled at a given time.
IRMx—Interrupt Request Mask 0–7
These bits determine whether an IRQx interrupt service request from an external source is
to be automatically generated to the core. Independent of the IRMx setting, the system
interface unit will automatically set the corresponding IRQx bit in the SIPEND register. See
Figure 12-2 for more information.
SIMASK
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = Disable automatic generation of an interrupt request to the CPU. You can monitor
1 = Enable automatic generation of an interrupt service request to the CPU, which may
the corresponding IRQx bit in the SIPEND register to implement interrupt polling.
then vector to an interrupt service routine. The EDx bits in the SIEL register
determine if the corresponding IRQx interrupt is falling edge-triggered or low logical
level triggered. The WMx field in the SIEL register determines if the corresponding
IRQx interrupt will cause the MPC823 to exit low-power mode.
IRM0 LVM0 IRM1 LVM1 IRM2 LVM2 IRM3 LVM3 IRM4 LVM4 IRM5 LVM5 IRM6 LVM6 IRM7 LVM7
R/W
16
0
0
Note: IRQ0 will generate a non-maskable interrupt even if its corresponding IRM0 bit
R/W
17
1
0
R/W
18
is not set.
2
0
Freescale Semiconductor, Inc.
R/W
For More Information On This Product,
19
3
0
R/W
20
MPC823 REFERENCE MANUAL
4
0
Go to: www.freescale.com
R/W
21
5
0
(IMMR & 0xFFFF0000) + 0x014
(IMMR & 0xFFFF0000) + 0x016
R/W
22
6
0
RESERVED
R/W
23
7
0
R/W
0
R/W
24
8
0
R/W
25
9
0
R/W
10
26
0
R/W
11
27
0
R/W
12
28
0
R/W
13
29
0
MOTOROLA
R/W
14
30
0
R/W
15
31
0

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