mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 371

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

EHTR—Extended Hold Time on Read
When this bit is set, it adds one clock cycle after a read from the current bank and any CPU
write or read to a different bank.
Bit 31—Reserved
This bit is reserved and must be set to 0.
15.3.1.3 MEMORY STATUS REGISTER. The memory status (MSTAT) register reports
parity and write-protect errors encountered during an external bus access initiated by the
memory controller. To clear a specific bit, write a one to it (writing zero has no effect).
PER0—Parity Error Bank 0
When this bit is set it indicates that a parity error was detected during a Bank 0 read cycle
initiated by the memory controller.
PER1—Parity Error Bank 1
When this bit is set it indicates that a parity error was detected during a Bank 1 read cycle
initiated by the memory controller.
PER2—Parity Error Bank 2
When this bit is set it indicates that a parity error was detected during a Bank 2 read cycle
initiated by the memory controller.
PER3—Parity Error Bank 3
When this bit is set it indicates that a parity error was detected during a Bank 3 read cycle
initiated by the memory controller.
PER4—Parity Error Bank 4
When this bit is set it indicates that a parity error was detected during a Bank 4 read cycle
initiated by the memory controller.
PER5—Parity Error Bank 5
When this bit is set it indicates that a parity error was detected during a Bank 5 read cycle
initiated by the memory controller.
MSTAT
RESET
FIELD
ADDR
R/W
BIT
0 = Timing is defined by the memory controller.
1 = Extended hold time is defined on the current read access.
PER0
R/W
0
0
PER1
R/W
1
0
PER2
R/W
2
0
Freescale Semiconductor, Inc.
PER3
For More Information On This Product,
R/W
3
0
PER4
R/W
MPC823 REFERENCE MANUAL
4
0
Go to: www.freescale.com
PER5
R/W
5
0
PER6
R/W
(IMMR & 0xFFFF0000) + 0x178
6
0
PER7
R/W
7
0
WPER
R/W
8
0
9
10
11
RESERVED
R/W
12
0
Memory Controller
13
14
15-15
15