mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 38

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
LIST OF ILLUSTRATIONS (Continued)
Figure
Page
Number
Title
Number
16-35. Timer Cascaded Mode Block Diagram........................................................ 16-76
16-36. SDMA Data Paths ....................................................................................... 16-83
16-37. SDMA Bus Arbitration ................................................................................. 16-84
16-38. IDMA Buffer Descriptor Ring ....................................................................... 16-91
16-39. Single-Address, Peripheral Write, Asynchronous TA................................ 16-103
16-40. Single-Address, Peripheral Write, Synchronous TA.................................. 16-104
16-41. Single-Address, Peripheral Read, Synchronous TA ................................. 16-105
16-42. IDMA Single-Address Burst Read or Write ............................................... 16-111
16-43. Serial Interface Block Diagram.................................................................. 16-113
16-44. Various Configurations With the TDM Channel......................................... 16-116
16-45. Enabling Connections Through the Serial Interface.................................. 16-117
16-46. Configuring the TDM with Static Frames................................................... 16-118
16-47. Configuring the TDM with Dynamic Frames.............................................. 16-119
16-48. Using the SWTR Bit .................................................................................. 16-120
16-49. Serial Interface RAM Dynamic Changes................................................... 16-125
16-50. Example of One Clock Delay from Sync to Data (RFSD = 01) ................. 16-130
16-51. Example of No Delay from Sync to Data (RFSD = 00) ............................. 16-130
16-52. Example of Clock Edge (CE) Effect When DSC = 0 ................................. 16-131
16-53. Example of Clock Edge (CE) Effect When DSC = 1 ................................. 16-131
16-54. Example of Frame Transmission Reception When
RFSD or TFSD = 0 and CD = 1 ................................................................. 16-132
16-55. Example of CE = 0 and FE Interaction, XFSD = 0 .................................... 16-133
16-56. IDL Bus Application Example .................................................................... 16-141
16-57. IDL Terminal Adaptor ................................................................................ 16-143
16-58. IDL Bus Signals......................................................................................... 16-144
16-59. GCI Bus Signals ........................................................................................ 16-147
16-60. Bank of Clocks .......................................................................................... 16-152
16-61. Baud Rate Generator Block Diagram........................................................ 16-154
16-62. Serial Communication Controller Block Diagram ...................................... 16-161
16-63. SCCx Memory Structure ........................................................................... 16-177
16-64. RTSx Output Delays Asserted for Synchronous Protocols ....................... 16-186
16-65. CTSx Output Delays Asserted for Synchronous Protocols ....................... 16-187
16-66. CTSx Lost in Synchronous Protocols........................................................ 16-188
16-67. Using CDx to Control Synchronous Protocol Reception ........................... 16-189
16-68. DPLL Receiver Block Diagram.................................................................. 16-191
16-69. DPLL Transmitter Block Diagram.............................................................. 16-191
16-70. DPLL Encoding Examples ........................................................................ 16-193
16-71. Serial IrDA Link ......................................................................................... 16-195
16-72. UART Character Format ........................................................................... 16-198
16-73. Two UART Multidrop Mode Configuration Examples................................ 16-206
16-74. SCC2 UART Receive Buffer Descriptor Example ..................................... 16-218
16-75. SCCx UART Interrupt Event Example....................................................... 16-224
MPC823 REFERENCE MANUAL
MOTOROLA
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