mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 734

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Communication Processor Module
IDL—Idle Sequence Status Changed
This bit indicates that a change in the status of the serial line has occurred. The real-time
status of the line can be read in the SCCS–ASYNC HDLC register.
TXE—TX Error
This bit indicates that an error has occurred on the transmitter channel.
BRKe—Break End
This bit indicates that the end of a break sequence has been found. This indication is set
when one idle bit is received after a break sequence.
BRKS—Break Start
This bit indicates that a break character has been received. This is the first break of a break
sequence. You will not receive multiple BRKS events if a long break sequence is detected.
RXF—RX Frame
This bit indicates that the SCCx ASYNC HDLC channel has received a complete frame. This
bit is set no sooner than two bit times after the last bit of the closing flag is received.
BSY—Busy Condition
This bit indicates that a frame has been received and discarded due to a lack of buffers.
TXB—Transmit Buffer
This bit indicates that a buffer with its I bit set has been transmitted on the SCCx ASYNC
HDLC channel. This bit is set no sooner than when the last bit of the closing flag begins its
transmission if the buffer is the last one in the frame. Otherwise, this bit is set after the last
byte of the buffer is written to the transmit FIFO.
RXB—RX Buffer
This bit indicates that a buffer (that is not the last in the frame with its I bit set) has been
received over the SCCx ASYNC HDLC channel.
MPC823 REFERENCE MANUAL
MOTOROLA
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