mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1031

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
19.2.1 The Video Controller Clock
The video controller master clock source can either be the LCDCLK, which is generated by
the system interface unit, or the external video clock signal (CLK). Refer to
Section 5.2.1 System Clock and Reset Control Register and Section 5.3.4.4 The LCD
Clocks for more information. LCDCLK is derived from the SPLL. If the external video clock
is enabled by setting the CSRC bit in the VCCR, you must provide an external video clock
(CLK) at the port D input.
FIFO
FIFO
Note: If an external video clock (CLK) is used, then the ratio between that external
DMA INTERFACE
clock and GCLK1 must not be greater than 1.25:1. For example, if your system
clock is 50MHz, then the CLK input cannot exceed 62.5MHz.
Figure 19-2. Video Controller Block Diagram
Freescale Semiconductor, Inc.
CONTROLLER
For More Information On This Product,
DMA
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
U-BUS
CONFIGURATION
REGISTERS
ACTIVE PIXELS
BACKGROUND
PIXELS
CONTROL
VIDEO
RAM
HSYNC
VSYNC
FIELD
BLANK
8-BIT DATA
Video Controller
19-3

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