mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 575

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.7.4.4 SERIAL INTERFACE RAM DYNAMIC CHANGES. The serial interface RAM has
two operating modes:
Dynamic changes allow the routing definition of a TDM to be modified while the serial
communication controllers and serial management controllers are connected to it. With fixed
routing, a change has three requirements that must be met before the new routing takes
effect:
Dynamic changes divide portions of the serial interface RAM into current-route and shadow
RAM. Once the current-route RAM is programmed, the time-slot assigner and serial
interface channels are enabled and time-slot assigner operation begins. When you need to
make a change in routing, you must program the shadow RAM with the new route and set
the CSRRA bit in the serial interface command register to receive and the CSRTA bit to
transmit. As a result, the serial interface exchanges the shadow RAM and the current-route
RAM as soon as the corresponding sync arrives and resets the appropriate CSRxA bit to
signify that the operation has completed. At this time, you can change the routing again.
Notice that the original current-route RAM is now the shadow RAM and vice versa.
Figure 16-49 illustrates an example of the shadow RAM exchange process.
If a TDM with dynamic changes is programmed, the initial current-route RAM addresses in
the serial interface RAM are as follows:
The shadow RAMs are at addresses:
• A time-division mulitplex channel with a static routing definition. The serial interface
• A time-division mulitplex channel that allows dynamic changes. The serial interface
• time-division mulitplex channel with a static routing definition. The serial interface RAM
• time-division mulitplex channel that allows dynamic changes. The serial interface RAM
• The serial communication controllers and serial management controllers connected to
• The serial interface routing must be modified.
• The serial communication controllers and serial management controllers connected to
• 0–31 RXA Route
• 64–95 TXA Route
• 32–63 RXA Route
• 96–127 TXA Route
RAM is divided into two parts—transmit (TX) and receive (RX).
RAM is divided into four parts—two transmits (TX) and two receives (RX).
is divided into four parts—two transmits (TX) and two receives (RX).
is divided into eight parts—four transmits (TX) and four receives (RX).
the time-slot assigner must be disabled.
the time-slot assigner must be reenabled.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
16-123