mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 311

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

TRANSFER START
RESERVATION PROTOCOL
DATA
MNEMONIC
KR/RETRY
D[0:31]
BDIP
STS
TS
Table 13-1. Bus Interface Signals (Continued)
Freescale Semiconductor, Inc.
PINS
32
For More Information On This Product,
1
1
1
1
MPC823 REFERENCE MANUAL
ACTIVE
High
Low
Low
Low
Low
Go to: www.freescale.com
I/O
I/O
O
O
O
O
I
I
I
I
Burst Data In Progress—Driven by the MPC823
when it owns the external bus. It is part of the burst
protocol. Asserted indicates that the second beat in
front of the current one is requested by the master.
This signal is negated prior to the end of a burst to
terminate the burst data phase early.
Used only for testing purposes.
Transfer Start —Driven by the MPC823 when it owns
the external bus.It indicates the start of a transaction
on the external bus.
Sampled by the MPC823 when an external device
initiates a transaction and the memory controller was
configured to handle external master accesses.
Special Transfer Start—Driven by the MPC823
when it owns the external bus. It indicates the start of
a transaction on the external bus or an internal
transaction in show cycle mode.
Kill Reservation/Retry —When a bus cycle is
initiated by a stwcx instruction that was issued by the
core to a nonlocal bus on which the storage
reservation has been lost, this signal is used by the
nonlocal bus interface to back-off the cycle. Refer to
Section 13.4.10 Storage Reservation Protocol.
For a regular transaction, this signal is driven by the
slave device to indicate that the MPC823 has to
relinquish ownership of the bus and retry the cycle.
Data Bus —The data bus has the following byte lane
assignments:
Data Byte
D[0:7]
D[8:15]
D[16:23]
D[24:31]
Driven by the MPC823 when it owns the external bus
and has initiated a write transaction to a slave device.
For single beat transactions, if external A[6:31] and
TSIZ[0:1] do not select the byte lanes for transfer,
they will not supply valid data.
Driven by the slave in a read transaction. For single
beat transactions, if external A[6:31] and TSIZ[0:1] do
not select the byte lanes for transfer, they will not be
sampled by the MPC823. It is also sampled by the
MPC823 when the external master acquires the bus.
Byte Lane
0
1
2
3
DESCRIPTION
External Bus Interface
13-5