mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 559

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

You must initialize the parameter RAM values before the channel is enabled. However, they
must only be modified when there is no DMA activity.
DCMR
RESET
RESET
• Buffer Address Pointer—The buffer address pointer (BAPR) contains 32 address bits
• Byte Count Register—The 32-bit byte count register (BCR) specifies the number of
• DMA Channel Mode Register—The 32-bit DMA channel mode register (DCMR)
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
of the destination buffer address used by the IDMA. The BAPR must be programmed
to burst-aligned address. In progressive mode, the BAPR is incremented by 16 bytes
after each transfer and it is incremented by 16 for each burst. In interlaced mode the
BAPR is incremented by 16 for each burst while it is within a line and then it is
incremented by the raw bytes register to point to the next line.
bytes to be transferred by the IDMA. The BCR is decremented by 16 bytes after each
transfer and must be programmed as a multiple of 16. In progressive mode, the IDMA
channel will terminate the transfer of a block of data if this register reaches zero during
operation.
controls the channel operation mode.
MB1—Must Be 1
For DMA operation, this bit must be set to 1.
Bits 1–2, 9
These bits are reserved and must be set to 0.
MB1
R/W
16
0
0
RESERVED
17
—
1
11, 16
R/W
0
18
2
Freescale Semiconductor, Inc.
—
31—Reserved
For More Information On This Product,
19
3
R/W
BO
0
20
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
21
5
(IMMR & 0xFFFF0000) + 0x3CCA
(IMMR & 0xFFFF0000) + 0x3CC8
R/W
AT
22
6
0
RESERVED
23
7
R/W
0
STR
R/W
24
8
0
25
9
RESERVED
Communication Processor Module
R/W
10
26
0
11
27
EDGE ITLC
R/W
12
28
0
R/W
13
29
0
14
30
BPR
R/W
16-107
0
15
31