mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 674

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
R—Ready
Bits 1 and 9–14—Reserved
These bits are reserved and must be set to 0.
W—Wrap (Final Buffer Descriptor in Table)
I—Interrupt
CR—Clear-to-Send Report
This bit allows you to have no delay between buffers transmitted in SCCx UART mode or a
more accurate CTSx lost error report and three bits of idle between buffers.
A—Address
This bit is only valid in multidrop mode. Either automatic or manual.
0 = The data buffer associated with this buffer descriptor is not ready to be transmitted.
1 = The data buffer, which you must prepare for transmission, has not been
0 = This is not the last buffer descriptor in the TX buffer descriptor table.
1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer
0 = No interrupt is generated after this buffer is serviced.
1 = The TX bit in the SCCE–UART register is set when this buffer is serviced by the
0 = The buffer following this buffer is transmitted with no delay (assuming it is ready),
1 = Normal CTSx lost error reporting and three bits of idle occur between back-to-back
0 = This buffer only contains data.
1 = Set by the core, this bit indicates that this buffer contains address characters. All
You are free to manipulate this buffer descriptor or its associated data buffer. The
communication processor module clears this bit after the buffer is transmitted or
after an error condition is encountered.
transmitted yet or is currently being transmitted. You cannot write any fields of this
buffer descriptor once this bit is set.
has been used, the communication processor module will transmit data from the
first buffer descriptor that TBASE points to in the table. The number of TX buffer
descriptors in this table are programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
communication processor module, which can cause an interrupt.
but the CT bit may not be set in the correct TX buffer descriptor or may not be set
at all in a CTSx lost condition. Asynchronous flow control, however, continues to
function normally.
buffers.
of the buffer data is transmitted as address characters.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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