mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 861

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
If both the REN and TEN bits are set in the SMCMR, the first falling edge of the SMSYNx
pin causes both the transmitter and receiver to achieve synchronization. To resynchronize
the transmitter or receiver, the SMCx transmitter/receiver can be disabled and reenabled
and the SMSYNx pin can be used again to resynchronize the transmitter or receiver. Refer
to Section 16.11.5 Disabling the SMCs On-the-Fly for a description of how to safely
disable and reenable a serial management controller. Simply clearing and setting the TEN
bit may not be sufficient.
SMSYNx
SMCLK
SMRXD
SMSYNx
SMTXD
SMCLK
NOTES:
1. SMCLK is an internal clock derived from an external clock pin or a baud rate generator.
2. This example shows the SMC receiver and transmitter enabled separately. If the REN
HUNT MODE
COMMAND
HERE OR
REN SET
and TEN bits were set at the same time, a single falling edge of SMSYNx would
synchronize both.
ENTER
ISSUED
HERE
TEN
SET
Figure 16-118. SMSYNx Pin Synchronization
Freescale Semiconductor, Inc.
1s ARE SENT
DETECTED
LOW HERE
For More Information On This Product,
SMSYNx
DETECTED
LOW HERE
SMSYNx
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
LOADED
TX FIFO
FIVE 1s ARE SENT
APPX.
HERE
FIRST BIT OF
DATA (LSB)
RECEIVE
CHARACTER
EQUALS 5
ASSUME
LENGTH
FIVE 1s
SMC1 RECEIVE DATA
FIRST BIT OF
CHARACTER
FIRST 5-BIT
SMC1 TRANSMIT DATA
TRANSMIT
(LSB)
Communication Processor Module
HERE IF TX FIFO
NOT LOADED IN
TRANSMISSION
COULD BEGIN
TIME
16-409

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