mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 360

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Memory Controller
15.2 ARCHITECTURE
The memory controller consists of three basic machines:
As illustrated in Figure 15-2, each bank can be assigned to any one of these machines via
the MS field in the base register. When a memory address matches the BA field of the base
register, the corresponding machine takes ownership of the external signals that control
access until the cycle terminates.
The general-purpose chip-select machine (GPCM) provides a glueless interface to EPROM,
SRAM, Flash EPROM, and other peripherals. General-purpose chip-select signals are
available on CS[0:7]. CS0 also functions as the boot chip-select signal that allows the CPU
to access the boot EPROM from reset. Each chip-select allows a maximum of 30 wait states.
• General-purpose chip-select machine
• User-programmable machine A
• User-programmable machine B
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
Figure 15-2. Memory Controller Machine Selection
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
MS FIELD
MS FIELD
MS FIELD
MS FIELD
MS FIELD
MS FIELD
MS FIELD
MS FIELD
USER-PROGRAMMABLE
USER-PROGRAMMABLE
GENERAL-PURPOSE
CHIP-SELECT
MACHINE A
MACHINE B
MACHINE
MOTOROLA

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