mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 917

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
16.13.7 Programming the I
16.13.7.1 I
the I
Bits 0–1—Reserved
These bits are reserved and must be set to 0.
REVD—Reverse Data
This bit determines the receive and transmit character bit order.
GCD—General Call Disable
This bit determines if the receiver will acknowledge a general call address.
FLT—Clock Filter
This bit determines if the I
PDIV—Pre Divider
This field determines the division factor of the clock before it is fed into the baud rate
generator. The clock source for the I
system interface unit.
I2MOD
RESET
FIELD
ADDR
R/W
BIT
2
0 = Normal operation. Most-significant bit of character transmitted and received first.
1 = Reverse data. Least-significant bit of character transmitted and received first.
0 = General call address is enabled.
1 = General call address is disabled.
0 = I2CLK is not filtered.
1 = I2CLK is filtered by a digital filter.
00 = Use the BRGCLK/32 as the input to the I
01 = Use the BRGCLK/16 as the input to the I
10 = Use the BRGCLK/8 as the input to the I
11 = Use the BRGCLK/4 as the input to the I
C operation mode and clock source.
2
C MODE REGISTER. The read/write I
0
RESERVED
R/W
0
Freescale Semiconductor, Inc.
1
For More Information On This Product,
2
C input clock is filtered to prevent spikes in a noisy environment.
MPC823 REFERENCE MANUAL
REVD
R/W
2
2
0
Go to: www.freescale.com
C Controller
2
C controller is the BRGCLK that is generated by the
(IMMR & 0xFFFF0000) + 0x860
GCD
R/W
3
0
2
2
2
C baud rate generator.
C baud rate generator.
2
2
C mode (I2MOD) register controls both
C baud rate generator.
C baud rate generator.
R/W
FLT
4
0
Communication Processor Module
5
PDIV
R/W
0
6
R/W
EN
16-465
7
0

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