mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 160

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

The PowerPC Core
6.6.9 Instruction Timing
The following table summarizes the different load/store instructions timing in the case of
zero wait state memory references on a parked bus. With external memory accesses,
pipelined external accesses are assumed.
String instructions are broken into a series of aligned bus accesses. Figure 6-8 illustrates
the maximum number of bus cycles needed for string instruction execution.
6.6.10 Stalling Storage Control Instructions
A storage control instruction waits one clock before it is taken.
6.6.11 Accessing Off-Core Special Registers
Access to special registers—mtspr and mfspr—implemented off-core is executed by the
load/store unit via the internal bus using a special cycle. Refer to Section 6.4.1.1 Physical
Location of Special Registers for detailed information. If the access terminates in a bus
error, then an implementation-dependent software emulation interrupt is taken. All write
operations to off-core special registers (mtspr) are previously synchronized. In other words,
the instruction is not taken until all prior instructions terminate.
Fixed-Point Single Target
Register Load (Aligned)
Fixed-Point Single Target
Register Store (Aligned)
Load/Store Multiple
NOTE: N denotes the number of registers transferred.
Figure 6-8. Number of Bus Cycles Needed For String Instruction Execution
INSTRUCTION TYPE
0C’h
00’h
04’h
08’h
10’h
14’h
18’h
Table 6-12. Load/Store Instructions Timing
Freescale Semiconductor, Inc.
For More Information On This Product,
0C
00
04
08
10
14
18
MPC823 REFERENCE MANUAL
DATA CACHE
0D
01
05
09
11
15
19
Go to: www.freescale.com
2 Clocks
1 Clock
1 + N
0A
0E
1A
02
06
12
16
LATENCY
0B
1B
03
07
0F
13
17
3 N
EXTERNAL
MEMORY
+
5 Clocks
1 Clock
+
N 1
--------------
3
+
2 BUS CYCLES
2 BUS CYCLES
3 BUS CYCLES
TRANSFERS
WORD
2 Clocks
2 Clocks
CACHE
DATA
1 + N
LOAD/STORE UNIT
CLEARED FROM
3 N
EXTERNAL
MEMORY
+
5 Clocks
5 Clocks
+
MOTOROLA
N 1
--------------
3
+