mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 696

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
F—First in Frame
This bit is set by the SCCx HDLC controller when this buffer is the first in a frame.
CM—Continuous Mode
DE—DPLL Error
This bit is set by the SCCx HDLC controller if a DPLL error occurs while this buffer is being
received. In decoding modes in which a transition is promised every bit, the DE bit is set
when a missing transition occurs.
LG—RX Frame Length Violation
This bit indicates when a frame length greater than the maximum defined for this channel is
recognized and only the maximum-allowed number of bytes (MFLR) is written to the data
buffer. This event is not reported until the RX buffer descriptor is closed, the RXF bit is set,
and the closing flag is received. The actual number of bytes received between flags is
written to the DATA LENGTH field of this buffer descriptor.
NO—RX Nonoctet Aligned Frame
This bit indicates that a frame has been received that contains a number of bits almost
divisible by eight.
AB—RX Abort Sequence
This bit indicates that a minimum of seven consecutive ones have been received when a
frame is received.
CR—RX CRC Error
This bit indicates that this frame contains a CRC error. The received CRC bytes are always
written to the receive buffer.
OV—Overrun
This bit indicates that a receiver overrun has occurred while a frame was being received.
CD—Carrier Detect Lost
This bit indicates that a carrier detect signal has been negated while a frame was being
received. This bit is only valid when working in NMSI mode.
0 = The buffer is not the first one in a frame.
1 = The buffer is the first one in a frame.
0 = Normal operation.
1 = The E bit is not cleared by the communication processor module after this buffer
descriptor is closed, thus allowing the associated data buffer to be automatically
overwritten next time the communication processor module accesses this buffer
descriptor. The E bit is cleared if an error occurs during reception, regardless of
how the CM bit is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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