mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 540

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.5.2.3 SDMA MASK REGISTER. The 8-bit read/write SDMA mask register (SDMR) has
the same bit format as the SDMA status register. If a bit in the SDMA mask register is a 1,
the corresponding interrupt in the event register is enabled. If the bit is zero, the
corresponding interrupt is masked.
SBER—SDMA Channel Bus Error Mask (SDMA function)
Bits 1–5—Reserved
These bits are reserved and must be set to 0.
DSP2—DSP Chain 2 Transmitter Interrupt Mask (DSP function)
DSP1—DSP Chain 1 Receiver Interrupt Mask (DSP function)
SDMR
RESET
FIELD
ADDR
R/W
BIT
0 = Disable the SDMA channel bus error interrupt.
1 = Enable the SDMA channel bus error interrupt.
0 = Disable the DSP chain 2 transmitter interrupt, as described in
1 = Enable the DSP chain 2 transmitter interrupt.
0 = Disable the DSP chain 1 receiver interrupt, as described in Section 16.3.3.3 DSP
1 = Enable the DSP chain 1 receiver interrupt.
Section 16.3.3.3 DSP Event Register.
Event Register.
SBER
R/W
0
0
Freescale Semiconductor, Inc.
1
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MPC823 REFERENCE MANUAL
2
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(IMMR & 0xFFFF0000) + 0x90C
RESERVED
R/W
3
0
4
5
DSP2
R/W
6
0
MOTOROLA
DSP1
R/W
7
0