mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 62

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

External Signals
2.1 THE SYSTEM BUS SIGNALS
The MPC823 system bus signals consist of all the lines that interface with the external bus.
Many of these lines perform different functions, depending on how you assign them. The
following input and output signals are identified by their mnemonic name and each signal’s
pin number can be found in Figure 2-1.
SIGNAL
GPL_B5
RD/WR
BURST
A[6:31]
TSIZ0
TSIZ1
BDIP
REG
TS
PIN NUMBER
See Table 2-2
breakout.
for pin
E15
C13
B10
A13
D10
F15
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Address Bus—This bidirectional three-state signal provides the address for the
current bus cycle. A6 is the most-significant signal for this bus. The signal is output
when an internal master on the MPC823 initiates a transaction on the external bus.
The signal is input when an external master initiates a transaction on the bus and it
is sampled internally to allow the memory controller/PCMCIA interface to control the
accessed slave device.
Transfer Size 0—When accessing a slave in the external bus, this three-state signal
is used (together with TSIZ1) by the bus master to indicate the number of operand
bytes waiting to be transferred in the current bus cycle. This signal is input when an
external master initiates a transaction on the bus and it is sampled internally to allow
the memory controller/PCMCIA interface to control the accessed slave device.
REG—When the access is initiated by an internal master to a slave under control of
the PCMCIA interface, this signal is output to indicate which space in the PCMCIA
card is currently accessed.
Transfer Size 1—This three-state signal is used (with TSIZ0) by the bus master to
indicate the number of operand bytes waiting to be transferred in the current bus
cycle. This signal is driven by the MPC823 when it is the owner of the bus. It is input
when an external master initiates a transaction on the bus and it is sampled internally
to allow the memory controller/PCMCIA interface to control the accessed slave
device.
Read Write—This three-state signal is driven by the bus master to indicate the
direction of the bus’s data transfer. A logic one indicates a read from a slave device
and a logic zero indicates a write to a slave device. This signal is driven by the
MPC823 when it is the owner of the bus. It is input when an external master initiates
a transaction on the bus and is sampled internally to allow the memory controller/
PCMCIA interface to control the accessed slave device.
Burst Transaction—This three-state signal is driven by the bus master to indicate
that the current initiated transfer is a burst one. This signal is driven by the MPC823
when it is the owner of the bus. It is input when an external master initiates a
transaction on the bus; this signal and is sampled internally to allow the memory
controller/PCMCIA interface to control the accessed slave device.
Burst Data in Progress —When accessing a slave device in the external bus, the
master on the bus asserts this signal to indicate that the data beat in front of the
current one is the one requested by the master. This signal is negated prior to the
expected last data beat of the burst transfer.
General-Purpose Line B5 —This signal is used by the memory controller when the
user programmable machine B (UPMB) takes control of the slave access.
Transfer Start—This three-state signal is asserted by the bus master to indicate the
start of a bus cycle that transfers data to or from a slave device. This signal is driven
by the master only when it has gained ownership of the bus. Every master should
negate this signal before the bus relinquishes. A pull-up resistor should be connected
to this signal to prevent a slave device from detecting a spurious bus accessing it
when no master is taking ownership of the bus.
This signal is sampled by the MPC823 when it is not the owner of the external bus
to allow the memory controller/PCMCIA interface to control the accessed slave
device. It indicates that an external synchronous master initiated a transaction.
Table 2-1. Signal Descriptions
MPC823 REFERENCE MANUAL
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DESCRIPTION
MOTOROLA