mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 262

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
11.6.3.2 MMU INSTRUCTION RAM ENTRY READ REGISTER 0. The MMU instruction
RAM entry read register 0 (MI_RAM0) contains the physical page number and page
attributes of an entry indexed by the ITLB_INDX field of the MI_CTR. This register is only
updated when you write to the MI_CAM register.
RPN—Real Page Number
These bits are the most-significant bits of the page’s physical address.
PS_B—Page Size
CI—Cache-Inhibit
When this bit is 0, it is not cache-inhibited.
APG—Access Protection Group
A maximum of 16 protection groups are supported and represented in one’s compliment
format.
MI_RAM0
NOTE: — = Undefined.
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
000 = 4K.
001 = 16K.
011 = 512K.
111 = 8M.
010 = Reserved.
100 = Reserved.
101 = Reserved.
110 = Reserved.
16
0
17
1
RPN
R
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
20
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
PS_B
21
R
5
22
6
23
CI
SPR 817
R
SPR 817
7
RPN
R
24
8
25
9
APG
R
10
26
11
27
Memory Management Unit
12
28
13
29
SFP
R
14
30
11-45
15
31

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