mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 181

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Storage Control Instructions:
isync
Order Storage Access:
eieio
Cache Control:
icbi
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
INSTRUCTIONS
Refer to Table 6-11 for details.
Refer to Section 6.4.1 Control Registers.
See Table 6-10 for details.
Where:
Blocking the multiply instruction is dependent on the subsequent instruction. For any subsequent
multiply instruction, the blockage is 1 clock and for any subsequent divide it is 2 clocks.
Assuming nonspeculative aligned access, on-chip memory, and available bus. For details, refer to
Section 6.6.5 Issuing Nonspeculative Load Instructions , Section 6.6.6 Executing Unaligned
Instructions , and Section 6.6.9 Instruction Timing .
Although a store (as well as mtspr for special registers external to the core) issued to the load/store
unit buffer frees the core pipeline, the next load or store will not actually be performed on the bus until
the bus is free.
DivisionBlockage
Table 8-1. Instruction Execution Timing (Continued)
DivisionLatency
Freescale Semiconductor, Inc.
Overflow
For More Information On This Product,
=
DivisionLatency
=
MPC823 REFERENCE MANUAL
=
NoOverflow
----------------------------------------------------------------------------------------------------------------------- -
Go to: www.freescale.com
x
-- - or
0
LATENCY
Serialize
MaxNegativeNumber
-------------------------------------------------------------- -
1
1
Overflow
3
1 –
+
34 divisorLength
------------------------------------------------------
BLOCKAGE
–
Serialize
2
1
1
4
EXECUTION
I-Cache
Branch
Instruction Execution Timing
LDST,
LDST
UNIT
Next Load or Store
Relative to All Prior
is Synchronized
INSTRUCTION
SERIALIZING
Load or Store
Yes
No
8-3