mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 170

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

7.3.7.3.1 System Reset Interrupt. A system reset interrupt occurs when the IRQ0 pin is
asserted and the following registers are set. Execution begins at physical address 0x100 if
the hard reset configuration word IIP bit is 1. Execution begins at physical address
0xFFF00100 if the hard reset configuration word IIP bit is 0.
SRR0—Save/Restore Register 0
Set to the effective address of the next instruction the processor executes if no interrupt
conditions are present.
SRR1—Save/Restore Register 1
Used to save the machine status prior to exceptions and to restore status when an rfi
instruction is executed.
MSR—Machine State Register
7.3.7.3.2 Machine Check Interrupt. A machine check interrupt indication is received from
the U-bus as a response to the address or data phase. It is usually caused by one of the
following conditions:
As defined in PowerPC Operating Environment Architecture (Book III) , machine check
interrupts are enabled when MSR
indication is received, the processor enters the checkstop state. The behavior of the core in
checkstop state is dependent on the working mode as defined in Section 20.4.2.1 Debug
Mode Enable vs. Debug Mode Disable. When the processor is in debug mode enable, it
enters the debug mode instead of the checkstop state. When in debug mode disable,
instruction processing is suspended and cannot be restarted without resetting the core.
An indication that can generate an automatic reset in this condition is sent to the system
interface unit. Refer to the Section 12 System Interface Unit for more details. If the
machine check interrupt is enabled (MSR
is recoverable and the following registers are set.
SRR0—Save/Restore Register 0
Set to the effective address of the instruction that caused the interrupt.
• The accessed address does not exist
• A data error is detected
1–4
10–15
Other
IP
ME
LE
Other
Set to 0.
Set to 0.
Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
No change.
No change.
Bit is copied from the ILE.
Set to 0.
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ME
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=1. If MSR
ME
=1) it is taken. If SRR1 Bit 30 =1, the interrupt
ME
= 0 and a machine check interrupt
PowerPC Architecture Compliance
RI
.
7-9