mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 953

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
16.15.4 Generating and Calculating an Interrupt Vector
All pending unmasked CPM interrupts are presented to the core in order of priority. The core
responds to an interrupt request by setting the IACK bit in the CIVR. The interrupt vector that
allows the core to locate the interrupt service routine is made available to the core by reading
the CIVR. For CPM interrupts, the CPM interrupt controller passes an interrupt vector
corresponding to the unmasked pending interrupt of the highest priority. The CPM interrupt
controller encoding of the five low-order bits of the interrupt vector is shown in Table 16-46.
EVENT
MASK
BIT
BIT
SCCM
SCCE
Figure 16-134. Interrupt Request Masking
Freescale Semiconductor, Inc.
For More Information On This Product,
(13 EVENT BITS)
13 INPUT
MPC823 REFERENCE MANUAL
OR
Go to: www.freescale.com
MASK
BIT
CIMR
CIPR
(28 CIPR BITS)
28 INPUT
Communication Processor Module
OR
REQUEST
TO THE IMB
AT THE
LEVEL
SPECIFIED
IN IRL2–IRL0
IN THE CICR.
16-501

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