mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 234

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

ITLB_INDX—Instruction TLB Index
This field acts as a pointer to the instruction TLB entry to be loaded. It is automatically
decremented at every instruction translation lookaside buffer update.
Bits 24–31—Reserved
These bits are reserved and must be set to 0. Ignored on write and returns a 0 on read.
11.6.1.2 MMU DATA CONTROL REGISTER. The MMU data control register (MD_CTR) is
a special register that is used to control the operation of the data memory management unit.
GPM—Group Protection Mode
PPM—Page Protection Mode
CIDEF—CI Default
This bit is the data cache attributes default value when the data MMU is disabled
(MSR
WTDEF—WT Default
This bit is the data cache attributes default value when the data MMU is disabled
(MSR
RSV2D—Reserve Two Data TLB Entries
MD_CTR
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = PowerPC mode.
1 = Domain manager mode.
0 = Page resolution protection.
1 = 1K resolution protection for a 4K page.
0 = DTLB_INDX decremented modulo 8.
1 = DTLB_INDX decremented modulo 6.
DR
DR
= 0).
= 0).
GPM
R/W
16
0
0
R/WR
PPM
17
1
0
RESERVED
CIDEF
R/W
R/W
18
2
0
0
Freescale Semiconductor, Inc.
WTDEF RSV2D
For More Information On This Product,
R/W
19
3
0
R/W
20
MPC823 REFERENCE MANUAL
4
0
Go to: www.freescale.com
TWAM
R/W
21
5
0
DTLB_INDX
PPCS
R/W
R/W
22
6
0
0
23
7
SPR 792
SPR 792
24
8
25
9
10
26
RESERVED
R/W
11
27
Memory Management Unit
0
RESERVED
R/W
0
12
28
13
29
14
30
11-17
15
31