mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 529

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.4.2.2 TIMER GLOBAL CONFIGURATION REGISTER. The 16-bit, memory-mapped,
read/write timer global configuration register (TGCR) contains configuration parameters that
are used by both timers. It allows simultaneous starting and stopping of any number of
timers as long as one bus cycle is used to access TGCR.
CAS4—Cascade Timers
FRZ4–FRZ1—Freeze
STP4–STP1 —Stop Timer
RST4–RST1—Reset Timer
Bit 4—Reserved
This bit is reserved and must be set to 0.
CAS2—Cascade Timers
TGCR
RESET
FIELD
ADDR
R/W
BIT
0 = Normal operation.
1 = Timers 3 and 4 are cascaded to form a 32-bit timer.
0 = The corresponding timer ignores the FRZ pin.
1 = Stops the corresponding timer if the FRZ pin is asserted by the core during
0 = Normal operation.
1 = Reduce the timer’s power consumption. This bit stops all clocks to the timer, except
0 = Reset the corresponding timer. A software reset is identical to an external reset.
1 = Enable the corresponding timer if the STPx bit is cleared.
0 = Normal operation.
1 = Timers 1 and 2 are cascaded to form a 32-bit timer.
breakpoint.
the clock from the U-Bus interface, which allows you to read and write the timer
registers. The clocks to the timer remain inactive until you clear this bit or a
hardware reset occurs.
CAS4
R/W
0
0
FRZ4
R/W
1
0
STP4
R/W
2
0
Freescale Semiconductor, Inc.
RST4
For More Information On This Product,
R/W
3
0
RES
R/W
MPC823 REFERENCE MANUAL
4
0
Go to: www.freescale.com
FRZ3
R/W
5
0
STP3
R/W
6
0
(IMMR & 0xFFFF0000) + 0x980
RST3
R/W
7
0
CAS2
R/W
8
0
FRZ2
R/W
9
0
Communication Processor Module
STP2
R/W
10
0
RST2
R/W
11
0
GM1
R/W
12
0
FRZ1
R/W
13
0
STP1
R/W
14
0
16-77
RST1
R/W
15
0