mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 167

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

PowerPC Architecture Compliance
7.2.4 Timebase
A description of the timebase register can be found in Section 12 System Interface Unit
and Section 5 Clocks and Power Control.
7.3 P
The MPC823 has an internal memory space that includes memory-mapped control registers
and memory that is used by various modules on the chip. This memory is part of the main
memory as seen by the core but cannot be accessed by any external system master.
7.3.1 The Branch Processor
7.3.1.1 MACHINE STATE REGISTER. The floating-point exception mode is ignored by the
MPC823. The IP bit initial state after reset is set as programmed by the reset configuration
specified in Section 12 System Interface Unit.
7.3.1.2 PROCESSOR VERSION REGISTER. The value of the PVR register’s version field
is x’0050’. The value of the revision field is x’0000’ and it is incremented each time the core
is revised so that software distinguishes between the core revisions.
7.3.1.3 BRANCH PROCESSORS INSTRUCTIONS. The core implements all the
instructions defined for the branch processor in the PowerPC User Instruction Set
Architecture Book I in the hardware. For the details about the performance of various
instructions, see Table 8-1 of this manual.
7.3.2 The Fixed-Point Processor
7.3.2.1 UNSUPPORTED REGISTERS. The following registers are not supported by the
MPC823. Refer to Section 7.3.3 Storage Model for more details.
7.3.2.2 ADDED REGISTERS. For a list of the added special purpose registers, see
Table 6-9.
7.3.3 Storage Model
Page sizes are 4K, 16K, 512K, and 8M and an optional sub-page granularity of 1K for 4K
pages in a maximum real memory size of 4G. Neither ordinary or direct-store segments are
supported.
7.3.3.1 ADDRESS TRANSLATION. If address translation is disabled (MSR
instruction accesses or MSR
real address and is passed directly to the memory subsystem. Otherwise, the effective
address is translated by using the translation lookaside buffer (TLB) mechanism of the
memory management unit (MMU). Instructions are not fetched from no-execute or guarded
storage and data accesses are not executed speculatively to or from the guarded storage.
SDR 1
EAR
IBAT0U
OWER
PC OPERATING ENVIRONMENT ARCHITECTURE (BOOK III)
IBAT2U
IBAT2L
IBAT3U
Freescale Semiconductor, Inc.
For More Information On This Product,
DR
=0 for data accesses), the effective address is treated as the
MPC823 REFERENCE MANUAL
DBAT1U
DBAT1L
DBAT2U
Go to: www.freescale.com
IBAT0L
IBAT1U
IBAT1L
IBAT3L
DBAT0U
DBAT0L
IR
DBAT2L
DBAT3U
DBAT3L
=0 for
MOTOROLA