mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1340

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

SDSR,
selecting a general system clock,
selecting a machine,
self-refresh mode, exiting,
sequence of interrupt detection,
sequencer unit, of the core,
serial communication controller 2
serial communication controller 3
serial communication controllers
memory map,
memory map,
AppleTalk mode
AppleTalk mode,
ASYNC HDLC mode
block diagram,
buffer descriptors
buffer descriptors,
clock glitches,
data synchronization register (DSR),
digital phase-locked loop,
disabling on-the-fly,
Ethernet mode
16-160
16-33
connectivity,
features,
operation,
programming,
commands,
configuration,
errors,
event register (SCCE-ASYNC HDLC),
features,
frame reception,
frame transmission,
implementation,
mode register (PSMR-ASYNC HDLC),
parameter RAM memory map,
programming guide,
receive buffer descriptor,
transmit buffer descriptor,
format,
address recognition,
collision handling,
commands,
configuration,
connecting to EEST,
errors,
event register,
features,
frame reception,
frame transmission,
16-266
16-315
281
276
,
16-87
16-275
16-333
16-176
16-263
16-266
16-316
3-9
3-9
16-262
16-194
16-161
16-274
16-327
15-4
16-264
16-262
16-273
16-327
16-265
16-175
16-343
16-196
16-270
16-267
16-321
15-43
16-332
6-4
16-266
16-320
Freescale Semiconductor, Inc.
16-283
16-329
16-318
16-190
,
For More Information On This Product,
16-266
6-14
16-277
5-17
16-279
MPC823 REFERENCE MANUAL
16-271
16-174
Go to: www.freescale.com
16-
16-
features,
general SCCx mode high register (GSMR_H),
general SCCx mode low register (GSMR_L),
HDLC bus controller
HDLC mode
initialization,
interrupts,
IrDA mode
IrDA,
16-163
16-168
hash table algorithm,
interpacket gap time,
loopback and full-duplex operation,
mask register,
mode register (PSMR-Ethernet),
operation,
parameter RAM memory map,
programming example,
receive buffer descriptor,
status register,
transmit buffer descriptor,
features,
memory map and programming,
commands,
errors,
event register (SCCE-HDLC),
frame reception,
frame transmission,
mask register (SCCM-HDLC),
mode register (PSMR-HDLC),
operation,
programming,
receive buffer descriptors,
status register (SCCS-HDLC),
transmit buffer descriptor,
data link layer,
high-speed
high-speed,
infrared interaction pulses,
infrared serial interaction pulse control
low-speed programming example,
low-speed,
middle-speed programming example,
middle-speed,
physical layer,
programming,
serial infrared mode register (IRMODE),
16-254
16-284
332
register (IRSIP),
295
programming example,
16-162
16-184
16-237
16-185
16-256
16-315
16-230
16-285
16-236
16-287
16-235
16-291
16-345
16-286
16-289
16-288
16-345
16-232
16-293
16-231
16-331
16-332
16-345
16-337
16-340
16-245
16-241
16-290
16-297
16-247
16-250
16-239
16-251
16-323
16-261
16-334
Index-27
16-294
16-
Index
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