mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1204

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
divwu
Assembler Syntax
Definition
Operation
Description
FIELD
FIELD
BIT
BIT
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0
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1
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B
2
Freescale Semiconductor, Inc.
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3
divwu.
divwuo
divwuo.
divisor
rD
rB. A 32-bit quotient is formed. The 32-bit quotient is placed into
rD. The remainder is not supplied as a result.
Both operands and the quotient are interpreted as unsigned
integers, except that if Rc = 1 the first three bits of CR0 field are
set by signed comparison of the result to zero. The quotient is
the unique unsigned integer that satisfies the equation—
dividend = (quotient
attempt is made to perform the division—<anything>
the contents of rD are undefined as are the contents of the LT,
GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE =
1 then OV is set.
The 32-bit unsigned remainder of dividing the contents of rA by
the contents of rB can be computed as follows:
divwu
mullw
subf
divwu
Divide Word Unsigned
dividend
The dividend is the contents of rA. The divisor is the contents of
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MPC823 REFERENCE MANUAL
4
dividend
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OE
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rB)
( r A)
rD,rA,rB (OE = 0 Rc = 0)
rD,rA,rB (OE = 0 Rc = 1)
rD,rA,rB (OE = 1 Rc = 0)
rD,rA,rB (OE = 1 Rc = 1)
rD,rA,rB
rD,rD,rA
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rD,rD,rB
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divisor
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divisor) + r (where 0
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D
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# rD = quotient
# rD = quotient * divisor
# rD = remainder
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459
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MPC823 Instruction Set—divwu
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12
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r < divisor). If an
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A
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0—then
B-51
RC
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