mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 706

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.9.17 The HDLC Bus Controller
The HDLC bus is an enhancement that makes it easy to implement an HDLC-based LAN
and other point-to-multipoint configurations. Most HDLC-based controllers only provide
point-to-point communications. The HDLC bus is based on the techniques used in the
CCITT ISDN I.430 and ANSI T1.605 standards for D channel point-to-multipoint operation
over the S/T interface. However, the HDLC bus is not fully compliant with I.430 or T1.605
and cannot be used to replace devices that implement these protocols. Instead, it is more
suited to fulfill the needs of non-ISDN LAN and point-to-multipoint configurations.
You must review the basic features of the I.430 and T1.605 before learning about the HDLC
bus. The I.430 and T1.605 define a method whereby eight terminals can be connected over
the D-channel of the S/T bus of ISDN. The protocol used at layer 2 is a variant of HDLC,
called LAPD. However, at layer 1, a method is provided that allows the eight terminals to
access the physical S/T bus so they can send frames to the switch.
To find out if a channel is clear, the S/T interface device looks at an “echo” bit on the line
designed to echo the last bit transmitted on the D channel. Depending on the “class” of the
terminal and the particular situation, the S/T interface device can wait for 7, 8, 9, or 10 ones
on the echo bit before allowing the LAPD frame to begin transmission. Once transmission
begins, the S/T chip monitors the data that is sent and if the echo bit matches the transmitted
data, transmission continues. If the echo bit is zero when the transmit bit is 1, then a collision
will occur between terminals and the station that transmitted a zero will no longer transmit.
The station that transmitted a one, however, continues as normal.
The I.430 and T1.605 provide a physical layer protocol that allows multiple terminals to
share the same physical connection. Where collisions are concerned, these protocols use
the bus efficiently because one station is always able to complete its transmission. Once a
station completes a transmission, it lowers its own priority to give other devices fair access
to the physical connection.
Note: After 5 bytes in the preamble have been transmitted, the TX buffer descriptor is
automatically closed. Once 16 bytes have been received, the RX buffer
descriptor is closed. Any data received after 16 bytes causes a busy
(out-of-buffers) condition since only one RX buffer descriptor is prepared.
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
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