mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1058

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

20.2.1 Basic Operation
20.2.1.1 THE INTERNAL HARDWARE. To make the events that occur in the machine
visible, a few dedicated pins are used. Also, a special bus cycle attribute called program
trace cycle is defined. The program trace cycle attribute is attached to all fetch cycles that
result from indirect flow changes. When program trace recording is required, you must
program the appropriate registers to ensure that these cycles are visible on the external bus.
The internal visible sync (VSYNC) signal, when asserted, forces all fetch cycles marked with
the program trace cycle attribute to be visible on the external bus, even if their data is found
in one of the internal devices. To enable the external hardware to properly synchronize with
the internal activity of the core, VSYNC assertion and negation forces the machine to
synchronize and marks the first fetch after the synchronization as a program trace cycle that
can be seen on the external bus. For more information about the activity of the external
hardware during program trace, refer to Section 20.2.1.2 The External Hardware
When the VSYNC signal is asserted, all fetch cycles marked with the program trace cycle
attribute become visible on the external bus. These cycles generate regular bus cycles when
the instructions reside in one of the external devices or address-only cycles when the
instructions are in an internal device. When the VSYNC signal is asserted, some
performance degradation occurs because of the additional external bus cycles. Since this
performance degradation is usually very small, you can program the machine to show all
indirect flow changes, perform these additional external bus cycles, and maintain the same
behavior when the VSYNC signal is asserted and negated. For more information, see
Section 20.6.2.5 Instruction Support Control Register .
Note: To keep the pin count of the chip as low as possible, the VSYNC signal is not
implemented as one of the chip’s external pins. Instead, it is asserted and
negated using the serial interface implemented in the development port. For
more information on this interface, refer to Section 20.4.3 The Development
Interface Port . Forcing the core to show all fetch cycles marked with the
program trace cycle attribute can be accomplished by either asserting the
VSYNC signal or by programming the ISCT_SER field in the instruction support
control (ICTRL) register. For more information, see Section 20.2.2 Controlling
Instruction Fetch Show Cycles .
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Development Capabilities and Interface
20-3