MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 85

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3.8
This section presents V2 processor instruction execution times in terms of processor core clock
cycles. The number of operand references for each instruction is enclosed in parentheses following
the number of processor clock cycles. Each timing entry is presented as C(R/W) where:
This section includes the assumptions concerning the timing values and the execution time details.
3.8.1
For the timing data presented in this section, the following assumptions apply:
Freescale Semiconductor
Table 3-11. D1 Local Memory Hardware Configuration Information Field Description
• C is the number of processor clock cycles, including all applicable operand fetches and
• R/W is the number of operand reads (R) and writes (W) required by the instruction. An
1. The operand execution pipeline (OEP) is loaded with the opword and all required extension
2. The OEP does not experience any sequence-related pipeline stalls. For V2 ColdFire
13–12
11–8
writes, and all internal core cycles required to complete the instruction execution.
operation performing a read-modify-write function is denoted as (1/1).
words at the beginning of each instruction execution. This implies that the OEP does not
wait for the instruction fetch pipeline (IFP) to supply opwords and/or extension words.
processors, the most common example of this type of stall involves consecutive store
operations, excluding the MOVEM instruction. For all STORE operations (except
MOVEM), certain hardware resources within the processor are marked as “busy” for two
processor clock cycles after the final DSOC cycle of the store instruction. If a subsequent
STORE instruction is encountered within this 2-cycle window, it will be stalled until the
resource again becomes available. Thus, the maximum pipeline stall involving
consecutive STORE operations is 2 cycles. The MOVEM instruction uses a different set
of resources and this stall does not apply.
Bits
7–4
3–0
Instruction Execution Timing
Timing Assumptions
ROM1SIZ
RAM1SIZ
DCSIZ
Name
DCA
Data cache associativity.
00 Four-way.
01 Direct mapped. (This is the value used for MCF5271)
Data cache size.
0000 No data cache. (This is the value used for MCF5271)
All other values do not apply for MCF5271.
RAM bank 1 size.
1000 64KB RAM. (This is the value used for MCF5271)
All other values do not apply for MCF5271
ROM bank 1 size.
0x0–0x3 No ROM. (This is the value used for MCF5271)
All other values do not apply for MCF5271.
MCF5271 Reference Manual, Rev. 2
Description
Instruction Execution Timing
3-19