MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 566

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
30.5
The ColdFire Family implements a low-level system debugger in the microprocessor hardware.
Communication with the development system is handled through a dedicated, high-speed serial
command interface. The ColdFire architecture implements the BDM controller in a dedicated
hardware module. Although some BDM operations, such as CPU register accesses, require the
CPU to be halted, other BDM commands, such as memory accesses, can be executed while the
processor is running.
30.5.1 CPU Halt
Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM
operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed
below in order of priority:
30-16
1. A catastrophic fault-on-fault condition automatically halts the processor.
2. A hardware breakpoint can be configured to generate a pending halt condition similar to
3. The execution of a HALT instruction immediately suspends execution. Attempting to
20–18/4–2
20/4
19/3
18/2
17/1
16/0
Bits
the assertion of BKPT. This type of halt is always first made pending in the processor.
Next, the processor samples for pending halt and interrupt conditions once per instruction.
When a pending condition is asserted, the processor halts execution at the next sample
point. See
execute HALT in user mode while CSR[UHE] = 0 generates a privilege violation
exception. If CSR[UHE] = 1, HALT can be executed in user mode. After HALT executes,
the processor can be restarted by serial shifting a
Execution continues at the instruction after HALT.
Background Debug Mode (BDM)
Name
EPC
EAx
PCI
Section 30.6.1, “Theory of
Table 30-15. TDR Field Descriptions (Continued)
Enable address bits. Setting an EA bit enables the corresponding address breakpoint.
Clearing all three bits disables the breakpoint.
EAI
EAR
EAL
Enable PC breakpoint. If set, this bit enables the PC breakpoint.
Breakpoint invert. If set, this bit allows execution outside a given region as defined by PBR
and PBMR to enable a trigger. If cleared, the PC breakpoint is defined within the region
defined by PBR and PBMR.
Enable address breakpoint inverted. Breakpoint is based outside the range
between ABLR and ABHR.
Enable address breakpoint range. The breakpoint is based on the inclusive range
defined by ABLR and ABHR.
Enable address breakpoint low. The breakpoint is based on the address in the
ABLR.
MCF5271 Reference Manual, Rev. 2
Operation.”
Description
GO
command into the debug module.
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