MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 376

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.2.5.3 Ethernet Transmit Buffer Descriptor (TxBD)
Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s
TxBDs. The Ethernet controller confirms transmission by clearing the ready bit (R bit) when
19-32
1
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 2
Offset + 6
0ffset + 4
The receive buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible
by 16. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
Word
Table 19-28. Receive Buffer Descriptor Field Definitions (Continued)
Whenever the software driver sets an E bit in one or more receive
descriptors, the driver should follow that with a write to RDAR.
15–0
15–0
15–0
Bits
8
7
6
5
4
3
2
1
0
Field Name
A[31:16]
A[15:0]
Length
Data
MC
NO
CR
OV
BC
LG
TR
—
M
MCF5271 Reference Manual, Rev. 2
Miss. Written by the FEC. This bit is set by the FEC for frames that were
accepted in promiscuous mode, but were flagged as a “miss” by the internal
address recognition. Thus, while in promiscuous mode, the user can use the
M-bit to quickly determine whether the frame was destined to this station.
This bit is valid only if the L-bit is set and the PROM bit is set.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
Will be set if the DA is broadcast (FF-FF-FF-FF-FF-FF).
Will be set if the DA is multicast and not BC.
Rx frame length violation. Written by the FEC. A frame length greater than
RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is set. The
receive data is not altered in any way unless the length exceeds 2032 bytes.
Receive non-octet aligned frame. Written by the FEC. A frame that contained
a number of bits not divisible by 8 was received, and the CRC check that
occurred at the preceding byte boundary generated an error. This bit is valid
only if the L-bit is set. If this bit is set the CR bit will not be set.
Reserved.
Receive CRC error. Written by the FEC. This frame contains a CRC error
and is an integral number of octets in length. This bit is valid only if the L-bit
is set.
Overrun. Written by the FEC. A receive FIFO overrun occurred during frame
reception. If this bit is set, the other status bits, M, LG, NO, CR, and CL lose
their normal meaning and will be zero. This bit is valid only if the L-bit is set.
Will be set if the receive frame is truncated (frame length > 2032 bytes). If
the TR bit is set the frame should be discarded and the other error bits should
be ignored as they may be incorrect.
Data length. Written by the FEC. Data length is the number of octets written
by the FEC into this BD’s data buffer if L = 0 (the value will be equal to
EMRBR), or the length of the frame including CRC if L = 1. It is written by the
FEC once as the BD is closed.
RX data buffer pointer, bits [31:16]
RX data buffer pointer, bits [15:0]
NOTE
Description
1
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