MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 504

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Message Digest Hardware Accelerator (MDHA)
26.2.7
The MDIN provides temporary storage for data to be used during hashing. The FIFO is a write
only register and attempting to read from this register will always return 0. If the FIFO is written
to when the FIFO Level is full then an interrupt request is generated and the MDISR[IFO] bit will
be set. The MDSR[IFL], described in
polled to monitor how many 32-bit longwords are currently resident in the FIFO.
26.2.8
The MDHA message digest registers 0 consist of five 32-bit registers (MDA0, MDB0, MDC0,
MDD0, and MDE0). These registers store the five (SHA-1) or four (MD5) 32-bit longwords that
are the final answer (digest/context) of the hashing process. Message digest data may only be read
if the MDSR[DONE] bit is set. Any reads prior to this result is an early read error (MDISR[ERE]).
The message digest registers will always return all zeros when an error is generated. Each word
(4 bytes) in the MDx0 is assumed to be in little endian byte order for all reads/writes. All
corrections will be done internal. This register is cleared when the MDHA is reset or re-initialized.
The reset values for the registers are the algorithms defined chaining variable values.
26.2.9
The MDMDS is a 32-bit register which, when read, will store the size of the current hash
operation. This register is also used to write in the data size from a resumed hash operation. This
data size will be added to the MDDSR to complete the auto pad step.
26-12
Address
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address
Reset
W
R
W
R
31
MDHA Input FIFO (MDIN)
MDHA Message Digest Registers 0 (MDx0)
MDHA Message Data Size Register (MDMDS)
31
IPSBAR + 0x19_0038 (MDC0); IPSBAR + 0x19_003C (MDD0); IPSBAR + 0x19_0040 (MDE0)
Figure 26-9. MDHA Message Data Size Register (MDMDS)
Figure 26-8. MDHA Message Digest Registers 0 (MDx0)
0xFEDC_BA98 (MDC0); 0x7654_3210 (MDD0); 0xF0E1_D2C3 (MDE0)
IPSBAR + 0x19_0030 (MDA0); IPSBAR + 0x19_0034 (MDB0);
0x0123_4567 (MDA0); 0x89AB_CDEF (MDB0);
MCF5271 Reference Manual, Rev. 2
MDA0, MDB0, MDC0, MDD0, MDE0
Section 26.2.4, “MDHA Status Register (MDSR),”
IPSBAR + 0x19_0044
Message Data Size
Freescale Semiconductor
0
can be
0