MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 165

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MCF5270CAB100

Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5270CAB100

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 8
Power Management
8.1
This chapter explains the low-power operation of the MCF5271.
8.1.1
The following features support low-power operation.
8.2
The PM programming model consists of one register:
8.2.1
The following subsection describes the PM registers.
Freescale Semiconductor
• Four modes of operation: Run, Wait, Doze, and Stop
• Ability to shut down most peripherals independently
• Ability to shut down the external CLKOUT pin
• The low-power control register (LPCR) specifies the low-power mode entered when the
1
2
3
IPSBAR Offset
S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result
in a cycle termination transfer error.
The CRSR, CWCR, and CWSR are described in the System Control Module. They are shown here only to warn
against accidental writes to these registers when accessing the LPICR.
The CCR is described in the Chip Configuration Module. It is shown here only to warn against accidental writes to
this register when accessing the LPCR.
0x00_0010
0x11_0004
STOP instruction is issued, and controls clock activity in this low-power mode.
Introduction
Features
Memory Map/Register Definition
Register Descriptions
Chip Configuration Register (CCR)
Core Reset Status
Register (CRSR)
Table 8-1. Chip Configuration Module Memory Map
[31:24]
2
MCF5271 Reference Manual, Rev. 2
Control Register
Core Watchdog
(CWCR)
[23:16]
3
Register (LPICR)
Interrupt Control
Low-Power
Reserved
[15:8]
Low-Power Control
Service Register
Register (LPCR)
Core Watchdog
(CWSR)
[7:0]
Access
S
S
1
8-1

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