MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 281

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Figure 14-9
when a DMA bus cycle begins. This delay may be longer, depending on DMA priority, bus
arbitration, and other factors.
properly enabled DREQn, the DMA acknowledge, and the activation of the channel for a transfer
where both the source and destination are mapped to chip select memories on the external bus.
Once the DMA module has detected the assertion of a properly-enabled DREQn, it responds with
a 1-cycle assertion of an acknowledge signal. This request/acknowledge handshake is provided so
the request can be negated.
Since bus timings can vary from device to device, the diagrams below are conditionalized for 5210
only. The information is really just a repeat from the EIM/FlexBus and SDRAMC chapters, so the
customers should not need this information. -MH
Freescale Semiconductor
Figure 14-9. DREQ
shows the minimum 4-clock cycle delay from when DREQn is sampled asserted to
DACKn
DREQn
CLKIN
A[31:0]
DREQn
DACKn
R/W
A[23:0]
CLKIN
TA
TS
CS
R/W
CS
TS
TA
0
0
1
1
n
Figure 14-9
Timing Constraints, Dual-Address DMA Transfer
2
MCF5271 Reference Manual, Rev. 2
2
3
3
shows the relationship between the assertion of a
4
4
5
Read
5
Read
6
6
7
7
8
8
Write
9
Write
9
10
Functional Description
10
11
14-17