MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 620

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Q
QSPI
R
Registers
Index-6
baud rate 23-6
memory map 23-9
operation
programming example 23-16
RAM
registers
Rx
signals 23-2
Tx
cache
CCM
chip select module
clock module
core
low-power modes 8-8
master mode 23-3
command 23-6
model 23-4
receive 23-5
transmit 23-5
address (QAR) 23-14
command RAM (QCRn) 23-14
data (QDR) 23-14
delay (QDLYR) 23-11
interrupt (QIR) 23-12
mode (QMR) 23-9
wrap (QWR) 23-12
RAM 23-5
delays 23-7
length 23-8
RAM 23-5
access control 0–1 (ACRn) 3-8
control (CACR) 3-7
chip configuration (CCR) 9-4
chip identification (CIR) 9-7
reset configuration (RCON) 9-5
address (CSARn) 16-7
control (CSCRn) 16-9
mask (CSMRn) 16-8
synthesizer control (SYNCR) 7-8
synthesizer status (SYNSR) 7-11
address (An) 3-3
condition code (CCR) 3-4
data (Dn) 3-2
program counter (PC) 3-3
stack pointer (A7) 3-3
status register (SR) 3-6
vector base (VBR) 3-7
,
5-7
,
3-7
,
5-10
MCF5271 Reference Manual, Rev. 2
debug
DMA controller
EMAC
EPORT
Ethernet
GPIO
address attribute trigger (AATR) 30-7
address breakpoint (ABLR, ABHR) 30-8
configuration/status (CSR) 30-9
data breakpoint/mask (DBR, DBMR) 30-12
program counter breakpoint/mask
trigger definition (TDR) 30-14
byte count (BCRn) 14-8
control (DCRn) 14-10
destination address (DARn) 14-8
request control (DMAREQC) 14-6
source address (SARn) 14-7
status (DSRn) 14-9
mask (MASK) 4-11
status (MACSR) 4-6
data direction (EPDDR) 15-4
flag (EPFR) 15-6
pin assignment (EPPAR) 15-3
pin data (EPPDR) 15-6
port data (EPDR) 15-5
port interrupt enable (EPIER) 15-5
control (ECR) 19-13
descriptor group upper/lower address
descriptor individual upper/lower
descriptor individual upper/lower address
FIFO receive bound (FRBR) 19-25
FIFO receive start (FRSR) 19-26
FIFO transmit FIFO watermark (TFWR) 19-25
interrupt event (EIR) 19-9
interrupt mask (EIMR) 19-10
MIB control (MIBC) 19-17
MII management frame (MMFR) 19-14
MII speed control (MSCR) 19-16
opcode/pause duration (OPD) 19-21
physical address low (PALRn) 19-20
physical address low/high (PALR, PAUR) 19-20
receive buffer size (EMRBR) 19-28
receive control (RCR) 19-18
receive descriptor active (RDAR) 19-11
receive descriptor ring start (ERDSR) 19-27
transmit buffer descriptor ring start (ETSDR) 19-27
transmit control (TCR) 19-19
transmit descriptor active (TDAR) 19-12
drive strength control (DSCR_x) 12-27
pin assignment (PARx) 12-18
(PBR/PBMR) 30-13
(GAUR/GALR) 19-24
(IAUR/IALR) 19-23
(IAUR/IALR) 19-22
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