MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 475

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 25
I
25.1
This chapter describes the MCF5271 I
and I
25.2
I
exchange, minimizing the interconnection between devices. This bus is suitable for applications
that require occasional communication between many devices over a short distance. The flexible
I
development.
The interface is designed to operate up to 100 Kbps with maximum bus loading and timing. The
device is capable of operating at higher baud rates, up to a maximum of the internal bus clock
divided by 20, with reduced bus loading. The maximum communication length and the number of
devices that can be connected are limited by a maximum bus capacitance of 400 pF.
The I
data corruption in the event that multiple devices attempt to control the bus simultaneously. This
feature supports complex applications with multiprocessor control and can be used for rapid
testing and alignment of end products through external connections to an assembly-line computer.
25.3
The I
Freescale Semiconductor
2
2
2
C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
C bus allows additional devices to be connected to the bus for expansion and system
C Interface
• Compatibility with I
• Support for 3.3-V tolerant devices
2
2
2
C programming model registers. It also provides extensive programming examples.
C system is a true multiple-master bus; it uses arbitration and collision detection to prevent
C module has the following key features:
Introduction
Overview
Features
The I
protocol. For information on system configuration, protocol, and
restrictions, see The I
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to
Purpose I/O
2
C module is designed to be compatible with the Philips I
Module”) prior to configuring the I
2
C bus standard version 2.1
MCF5271 Reference Manual, Rev. 2
2
C Bus Specification, Version 2.1.
2
C module, including I
NOTE
NOTE
Chapter 12, “General
2
2
C protocol, clock synchronization,
C module.
2
C bus
25-1