MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 28

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

About This Book
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Chapter 5,
organization, configuration, and coherency. It describes cache operations and how the
cache interacts with other memory structures.
Chapter 6, “Static RAM
implementation. It covers general operations, configuration, and initialization. It also
provides information and examples of how to minimize power consumption when using the
SRAM.
Chapter 7, “Clock
describes clock module operation in low power modes.
Chapter 8, “Power
peripheral behavior in low power modes.
Chapter 9, “Chip Configuration Module
the two modes of chip operation: master mode and single-chip mode. This chapter provides
a description of signals used by the CCM and a programming model.
Chapter 10, “Reset Controller
module, detailing the different types of reset that can occur.
Chapter 11, “System Control Module
which provides the programming model for the System Access Control Unit (SACU), the
system bus arbiter, a 32-bit Core Watchdog Timer (CWT), and the system control registers
and logic.
Chapter 12, “General Purpose I/O
model of the general purpose I/O (GPIO) ports on the MCF5271.
Chapter 13, “Interrupt Controller
portion of the SCM. Includes descriptions of the registers in the interrupt controller
memory map and the interrupt priority scheme.
Chapter 14, “DMA Controller
(DMA) controller module. It provides an overview of the module and describes in detail its
signals and registers. The latter sections of this chapter describe operations, features, and
supported data transfer modes in detail.
Chapter 15, “Edge Port Module
including operation in low power mode.
Chapter 16, “Chip Select
including the operation and programming model, which includes the chip-select address,
mask, and control registers.
Chapter 17, “External Interface Module
conditions, bus arbitration, and reset operations.
Chapter 18, “Synchronous DRAM Controller
operation of the SDRAM controller. It begins with a general description and brief glossary,
and includes a description of signals involved in DRAM operations. The remainder of the
“Cache,” describes the MCF5271 cache implementation, including
Module,” describes the MCF5271’s different clocking methods. It also
Management,” describes the low power operation of the MCF5271 and
(SRAM),” describes the MCF5271 on-chip static RAM (SRAM)
Module,” describes the MCF5271 chip-select implementation,
MCF5271 Reference Manual, Rev. 2
Module,” describes the operation of the reset controller
Module,” describes the MCF5271 Direct Memory Access
(EPORT),” describes EPORT module functionality,
Modules,” describes operation of the interrupt controller
Module,” describes the operation and programming
(SCM),” describes the functionality of the SCM,
(EIM),” describes data-transfer operations, error
(CCM),” describes CCM functionality, detailing
Module,” describes the configuration and
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