MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 479

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

If the master receiver does not acknowledge the slave transmitter after a byte transmission, it
means end-of-data to the slave. The slave releases I2C_SDA for the master to generate a STOP or
START signal
25.4.5 STOP Signal
The master can terminate communication by generating a STOP signal to free the bus. A STOP
signal is defined as a low-to-high transition of I2C_SDA while I2C_SCL is at logical high (F). The
master can generate a STOP even if the slave has generated an acknowledgment at which point the
slave must release the bus. The master may also generate a START signal following a calling
address, without first generating a STOP signal. Refer to
25.4.6 Repeated START
A repeated START signal is a START signal generated without first generating a STOP signal to
terminate the communication. The master uses a repeated START to communicate with another
slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.
Various combinations of read/write formats are then possible:
Freescale Semiconductor
I2C_SDA
I2C_SCL
I2C_SDA by Transmitter
START
Signal
I2C_SDA by Receiver
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
(Figure
1
2
I2C_SCL
Calling Address
3
25-4).
Figure 25-4. Acknowledgement by Receiver
4
START Signal
5
Figure 25-5. Repeated START
6
MCF5271 Reference Manual, Rev. 2
lsb
7
Bit7
1
R/W
8
Bit6
ACK
2
Bit
9
Bit5
XX
3
Repeated
START
Signal
Bit4 Bit3 Bit2 Bit1
msb
4
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
A
1
5
Section 25.4.6, “Repeated START.”
2
New Calling Address
Stop
6
3
7
4
R/W
Bit0
5
8
6
9
lsb
7
I
2
R/W No
C System Configuration
8
ACK
Bit
9
STOP
Signal
25-5