MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 300

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chip Select Module
16-10
15–14
13–10
Bits
7–6
9
8
5
4
SRWS
Name
BSTR
BEM
IWS
AA
PS
—
Secondary Read Wait States. The number of wait states applied to all reads after the initial
one if properly enabled (SRSW is non-zero and CSCR[AA] = 1). The default value of this
field is secondary read wait states disabled. See
Operation,”
00 Secondary read wait states are disabled. Use CSCR[IWS] for all accesses.
01 0 wait states for the secondary read accesses
10 1 wait state for the secondary read accesses
11 2 wait states for the secondary read accesses
Initial Wait States. The number of wait states inserted before an internal transfer
acknowledge is generated (WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait
states). If AA = 0, TA must be asserted by the external system regardless of the number of
wait states generated. In that case, the external transfer acknowledge ends the cycle. An
external TA supercedes the generation of an internal TA.
Reserved, should be cleared.
Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge
for accesses specified by the chip select address.
0 No internal TA is asserted. Cycle is terminated externally.
1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn
Port size. Specifies the width of the data associated with each chip select. It determines
where data is driven during write cycles and where data is sampled during read cycles. See
Section 16.3.1.1.
00 32-bit port size. Valid data sampled and driven on D[31:0]
01 8-bit port size. Valid data sampled and driven on D[31:24]
1x 16-bit port size. Valid data sampled and driven on D[31:16]
Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables
that must be asserted during reads as well as writes. BEM can be set in the relevant CSCR
to provide the appropriate mode of byte enable in support of these SRAMs.
0 BS is not asserted for read. BS is asserted for data write only.
1 BS is asserted for read and write accesses.
Burst read enable. Specifies whether burst reads are used for memory associated with
each CSn.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst
1 Enables data burst reads larger than the specified port size, including longword reads
and the external system asserts an external TA before the wait-state countdown asserts
the internal TA, the cycle is terminated. Burst cycles increment the address bus between
each internal termination.
reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and
32-bit ports.
Table 16-7. CSCRn Field Descriptions
for timing diagrams.
MCF5271 Reference Manual, Rev. 2
Description
Section 16.3.2, “Enhanced Wait State
Freescale Semiconductor