MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 380

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.3.3 Microcontroller Initialization
In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is
asserted. After the microcontroller initialization sequence is complete, the hardware is ready for
operation.
Table 19-33
19.3.4 User Initialization (After Asserting ECR[ETHER_EN])
After asserting ECR[ETHER_EN], the user can set up the buffer/frame descriptors and write to
the TDAR and RDAR. Refer to
19.3.5 Network Interface Options
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for
10 Mbps Ethernet. The interface mode is selected by the RCR[MII_MODE] bit. In MII mode
(RCR[MII_MODE] = 1), there are 18 signals defined by the IEEE 802.3 standard and supported
by the EMAC. These signals are shown in
19-36
shows microcontroller initialization operations.
Table 19-33. Microcontroller Initialization
Signal Description
Transmit Enable
Section 19.2.5, “Buffer
Transmit Clock
Receive Clock
Transmit Data
Transmit Error
Carrier Sense
Initialize BackOff Random Number Seed
MCF5271 Reference Manual, Rev. 2
Collision
Initialize Transmit Ring Pointer
Initialize FIFO Count Registers
Table 19-34. MII Mode
Initialize Receive Ring Pointer
Clear Transmit FIFO
Activate Transmitter
Clear Receive FIFO
Activate Receiver
Table 19-34
Description
EMAC pin
ETXD[3:0]
below.
ETXCLK
ERXCLK
Descriptors” for more details.
ETXEN
ETXER
ECOL
ECRS
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