MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 327

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

18.3.3 DRAM Controller Mask Registers (DMR0/DMR1)
The DMRn,
18.3.4 General Synchronous Operation Guidelines
To reduce system logic and to support a variety of SDRAM sizes, the DRAM controller provides
SDRAM control signals as well as a multiplexed row address and column address to the SDRAM.
18.3.4.1 Address Multiplexing
Table 18-7
possible address connection configurations can be derived from this table.
Freescale Semiconductor
Address
Reset
Reset
31–18
17–9
Bits
7-1
8
0
W
W
R
R
shows the generic address multiplexing scheme for SDRAM configurations. All
—
31
15
Figure
0
0
Name
BAM
—
30
14
WP
0
0
—
—
V
Figure 18-4. DRAM Controller Mask Registers (DMRn)
18-4, includes mask bits for the base address and for address attributes.
—
29
13
0
0
Base address mask. Masks the associated DACRn[BA]. Lets the DRAM controller connect
to various DRAM sizes. Mask bits need not be contiguous (see
Example.”)
0 The associated address bit is used in decoding the DRAM hit to a memory block.
1 The associated address bit is not used in the DRAM hit decode.
Reserved, should be cleared.
Write protect. Determines whether the associated block of DRAM is write protected.
0 Allow write accesses
1 Prohibit write accesses. The DRAM controller deasserts the external DRAMW (Write
Reserved, should be cleared.
Valid. Cleared at reset to ensure that the DRAM block is not erroneously decoded.
0 Do not decode DRAM accesses.
1 Registers controlling the DRAM block are initialized; DRAM accesses can be decoded.
Enable) signal and an access error exception occurs.
—
28
12
0
0
Table 18-6. DMRn Field Descriptions
IPSBAR + 0x00_004C (DMR0); 0x00_0054 (DMR1)
—
27
11
0
0
MCF5271 Reference Manual, Rev. 2
—
26
10
0
0
25
—
0
0
9
BAM
WP
—
24
0
8
23
—
Description
0
0
7
—
22
6
0
0
—
21
0
0
5
—
20
0
0
4
Section 18.4, “SDRAM
Memory Map/Register Definition
—
19
0
0
3
—
18
0
0
2
17
0
0
0
0
1
16
V
0
0
0
0
18-9