MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 564

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
Figure 30-9
using the WDEBUG instruction and via the BDM port using the wdmreg command.
30.4.7 Trigger Definition Register (TDR)
The TDR, shown in
corresponds with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers within the
debug module. The TDR controls the actions taken under the defined conditions. Breakpoint logic
may be configured as a one- or two-level trigger. TDR[31–16] define the second-level trigger and
bits 15–0 define the first-level trigger.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor
mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port
using the
30-14
DRc[4:0]
Reset
Reset
31–0
Bits
W
W
R
R
WDMREG
shows PBMR. PBMR is accessible in supervisor mode as debug control register 0x09
—
—
31
15
Figure 30-10. Program Counter Breakpoint Mask Register (PBMR)
The debug module has no hardware interlocks, so to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded,
disable TDR (by clearing TDR[29,13])before defining triggers.
Name
Mask
—
—
30
14
command.
Table
29
—
13
—
PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be
compared to the appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
30-11, configures the operation of the hardware breakpoint logic that
—
—
Table 30-14. PBMR Field Descriptions
28
12
27
—
—
11
MCF5271 Reference Manual, Rev. 2
—
—
26
10
—
—
25
9
NOTE
—
—
24
8
Mask
Mask
0x09
—
—
23
Description
7
—
—
22
6
—
—
21
5
20
—
—
4
—
—
19
3
Freescale Semiconductor
18
—
—
2
—
—
17
1
—
—
16
0