MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 65

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

2.3.14 Power and Ground Pins
The pins described in
provided for adequate current capability. All power supply pins must have adequate bypass
capacitance for high-frequency noise suppression.
2.4 External Boot Mode
When booting from external memory, the address bus, data bus, and bus control signals will
default to their bus functionalities as shown in
listed in
Freescale Semiconductor
PLL Analog Supply
Positive Supply
Positive Supply
Ground
Test
PLL Test
Table 2-17. Default Signal Functions After System Reset (External Boot Mode)
Signal Name
Signal Name
Table 2-14
A[23:0]
D[31:0]
BS[3:0]
OE
TA
TEA
R/W
TSIZ[1:0]
will operate as described above. All other signals will default to GPIO inputs.
Table 2-16
VDDPLL,
VSSPLL
VDDO
VDD
VSS
TEST
PLL_TEST
Abbreviation
Abbreviation
Signal
Table 2-16. Power and Ground Pins
provide system power and ground to the chip. Multiple pins are
MCF5271 Reference Manual, Rev. 2
Dedicated power supply signals to isolate the sensitive PLL analog
circuitry from the normal levels of noise present on the digital power
supply.
These pins supply positive power to the I/O pads
These pins supply positive power to the core logic.
This pin is the negative supply (ground) to the chip.
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of test
functions.
Reserved for factory testing only and should be treated as a
no-connect (NC).
Table 2-15. Test Signals
A[23:0]
Reset
Table
High
High
High
High
—
—
—
2-17. As in single-chip mode, the signals
Function
Function
I/O
I/O
O
O
O
O
O
I
I
.
External Boot Mode
I/O
I/O
I
I
I
I
I
2-15