MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 236

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

General Purpose I/O Module
12-20
11–10
Bits
15
14
13
12
9
8
7
6
5
4
PAR_TSIZ1 TSIZ[1] Pin Assignment Bits
PAR_TSIZ0 TSIZ[0] Pin Assignment Bit
PAR_RWB R/W Pin Assignment Bit
PAR_TEA
PAR_OE
PAR_TA
Name
—
—
—
—
—
Table 12-10. PAR_BUSCTL Field Descriptions
Reserved, should be cleared.
OE Pin Assignment Bit
The PAR_OE bit configures the OE pin for its primary function or GPIO.
0 OE pin configured for GPIO
1 OE pin configured for external bus OE function
Reserved, should be cleared.
TA pin assignment. The PAR_TA bit configures the OE pin for its primary function or GPIO.
0 TA pin configured for GPIO
1 TA pin configured for external bus TA function
TEA pin assignment. The PAR_TEA field configures the TEA pin for its primary functions
or GPIO.
0x TEA pin configured for general purposeI/O
10 TEA pin configured for DMA request 1 (DREQ1) function
11 TEA pin configured for external bus TEA function
Reserved, should be cleared
The PAR_RWB bit configures the R/W pin for its primary function or GPIO.
0 R/W pin configured for GPIO
1 R/W pin configured for external bus read/write function
Reserved, should be cleared
The PAR_TSIZ1 bit configures the TSIZ[1] pin for its primary functions or GPIO.
0 TSIZ[1] pin configured for GPIO
1 TSIZ[1] pin configured for external bus TSIZ1 function or DMA acknowledge 1 function
NOTE: The selection between the TSIZ function and DMA function on each of the
TSIZ[1:0] pins is determined by the value of the SZEN field in the CIM chip configuration
register. Please refer to the
information on chip configuration and the SZEN bit.
Reserved, should be cleared
The PAR_TSIZ0 bit configures the TSIZ[0] pin for its primary functions or GPIO.
0 TSIZ[0] pin configured for GPIO
1 TSIZ[0] pin configured for external bus TSIZ0 function or DMA acknowledge 0 function
NOTE: The selection between the TSIZ function and DMA function on each of the
TSIZ[1:0] pins is determined by the value of the SZEN field in the CIM chip configuration
register. Please refer to the
information on chip configuration and the SZEN bit.
MCF5271 Reference Manual, Rev. 2
Chapter 9, “Chip Configuration Module
Chapter 9, “Chip Configuration Module (CCM)”
Description
(CCM)” for more
Freescale Semiconductor
for more